StrichLux/CORE

The StrichLux Core is the "motherboard" of the system, that holds the framebuffers and lets the I/O modules talk to each other. It also holds the "transform engine", which is the FPGA that can do various transforms between the input and output.

Project Log

• 2012-06-15: 80% done assembling the first board.
• 2012-06-10: Started writing firmware, basic structure is in place and input module controller is 80% ready with very basic functionality (only WRITE command supported).
• 2012-05-27: Ordered boards from MyRO PCB. Parts are here already.
• 2012-05-26: Waiting to get PWR-DC5 and IO-ETH boards done to send all 3 off to get made at once.
• 2012-05-23: Found the power switch would interfere with the power jack, replaced with a vertical switch to resolve this issue.
• 2012-05-20: Routing complete, will wait to send board so I can review it again tomorrow.
• 2012-05-15: Routing continues, 30 airwires to go.
• 2012-05-08: EAGLE purchase went through, board routing started.
• 2012-05-07: Ran checklist, completed last few changes. Rev. 1 schematic complete, board layout started (but stuck until my EAGLE purchase goes through, as the board is 160x100mm).
• 2012-05-06: Schematic complete, checklist still needs to be run.
• 2012-05-05: Started working on the schematic.
• 2012-05-04: Started putting together specs/BOM.

Project Ideas

• Required I/O
  • 4 Input modules (one SPI slave transceiver and one I2C master transceiver each)
  • 4 output modules (one SPI slave transceiver and one I2C master transceiver each)
  • RS232 and USB for troubleshooting and configuring the core board itself
  • 1 Power module (one I2C master transceiver)
• Local framebuffer memory
  • Dual-port memory would be best so the output and input sections can both deal with it independently
  • 8 bits per frame * 512 channels per universe * 4 universes = 16kbit (2kbyte) of framebuffer memory required
    • Twice that for double-buffering would be awesome, so 32kbit/4kbyte of dual-port memory wanted
  • Split into 4 channels, so each block would be 8kbit/1kbyte
  • Reading/writing needs to happen in parallel for each block
• Looking at using the LFXP2-8E-5TN144C FPGA
  • 5 series is ~$5 cheaper but only has 3 sysDSP blocks, given the 4 channel system, 4 blocks seems a better fit

Revision 1 Issues

• Resistor packs for status LEDs are wrong footprint
• Power Module connector footprint needs tweaking to move pads further apart, solder bridges under the connector are almost impossible to avoid as it is
• Schematic lists ferrite chips as L1-L4, BOM as FB1-FB4