Difference between revisions of "ECLair"

From Hackstrich
(First parts of the microcode worked out.)
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| Register Load from Z
 
| Register Load from Z
 
| 000 - None<br>001 - A<br>010 - B<br>011 - C<br>100 - D<br>101 - SP
 
| 000 - None<br>001 - A<br>010 - B<br>011 - C<br>100 - D<br>101 - SP
 +
|-
 +
| 20-23
 +
| 4
 +
| ALU Operation
 +
| 1111 - Z=X
 
|}
 
|}
  
 
[[Category:Current Projects]]
 
[[Category:Current Projects]]

Revision as of 20:41, 5 December 2012

ECLair is a long-term project to build an ECL minicomputer.

Project Status

  • 2012-12-04: Started the logical diagram and the microcode layout.
  • 2012-12-01/02: Spent the weekend reading Bit-Slice Microprocessor Design.
  • 2012-11-24: Basic ideas/architecture starting to get put together.

Architecture Overview

  • MECL-based
  • 25MHz main clock
  • 8-bit data width
  • 24-bit physical address, 16-bit virtual address
  • DMA support (at least for front panel, maybe one other DMA channel?)
  • Microcoded, running control store in SRAM for speed
    • Unless I can find equally-fast EPROMs
    • Copied to SRAM from EPROM before the system starts

Microcode Layout

Bit # Width Function Details
0 1 MC Addr Source low = microcode bits, high = IR
1 1 Jump MC Addr Microcode sequencer load
2-10 8 MC Jump Address Used if bit 0 = low
11 1 MDR Source low = data bus, high = Z
12 1 MDR Load MDR latch load
13 1 MAR Load MAR latch load from Z
14 1 IR Load IR latch load from data bus
15 1 PC Increment Increment PC by 1
16 1 PC Load PC counter load from Z
17-19 3 Register Load from Z 000 - None
001 - A
010 - B
011 - C
100 - D
101 - SP
20-23 4 ALU Operation 1111 - Z=X