Difference between revisions of "TileDriver"
From Hackstrich
(Created page with "TileDriver is a board to drive HUB75 type RGB matrix panels from an SPI bus. It contains a framebuffer and interface circuitry to allow slower CPUs like an AVR or PIC to drive th...") |
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== Project Status == | == Project Status == | ||
| + | * 2015-12-18: Started implementing the dual-port RAM controller (with an EBR RAM backend for simplicity in the first version, rather than SDRAM like the real one will use). Works reliably if the RAM controller clock is 4x the main clock, but not 2x like it should. At 2x it sometimes works and sometimes acts weird, likely some kind of phase thing. Needs more troubleshooting. Have also only tested it at human-visible clock rates, need to get the logic analyzer out and test it at tens of MHz still. | ||
| + | * 2015-12-01: Fixed the missing-MSB error, was actually in the ruby code not the hardware/verilog! The SPI clock phase in the code driving the Bus Pirate was wrong, so the MSB was getting chopped off. Fixed and gradients look good now. | ||
| + | * 2015-11-28: Many speed and usability improvements in tilesend, now takes any image format and puts it on the display. Implemented gamma correction which makes the image look much better overall. Discovered that brightness levels are "wrapping around" and anything >127 goes back to zero brightness and ramps up again from there, indicating an MSB is getting chopped off somewhere. Logically analyzing r_value_a it seems bits 0 and 1 are always the same, which also doesn't seem right. Ran out of time after this point, need to pick back up here next time. Wrote a quick 'tilegradient' tool to generate a 0-255 gradient for troubleshooting. | ||
| + | * 2015-10-03: Build a breakout board for the tile connection to enable hooking a logic analyzer up to all the signals. Got SPI-to-tile working for a full display! Using the internal EBR in the CPLD right now, still need to fix up a lot of messy code and get the framebuffer into the external SDRAM, but it's getting there. | ||
| + | * 2015-09-26: Got the first 3 bytes of RAM used to set the colour of the whole screen, which is a start. | ||
| + | * 2015-09-19: Got the BCM working so each colour can now be set to any brightness via the DIP switches. | ||
| + | * 2015-09-18: Got the basic hardware assembled on the MachXO dev board (connector for tile, 3x3 DIP switches to set colours for testing). Screen is successfully being driven with a single hardcoded colour over the whole display. | ||
| + | * 2015-09-16: Received 32x32 video tile and MachXO dev board to prototype this. | ||
* 2015-09: Started putting idea together to use in the future BRCRD Scoreboard project. | * 2015-09: Started putting idea together to use in the future BRCRD Scoreboard project. | ||
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** 640x640x24bpp can update at 5fps, still fine for static data displays | ** 640x640x24bpp can update at 5fps, still fine for static data displays | ||
| − | [[Category: | + | == Gallery == |
| + | <gallery widths=160px> | ||
| + | Image:TileDriver-FirstLight.jpg|First light from the TileDriver code on the dev board. | ||
| + | Image:TileDriver-FirstDimming.jpg|First successful BCM-based dimming. | ||
| + | Image:TileDriver-FirstHalfDisplay.jpg|First half image display. | ||
| + | Image:TileDriver-FirstFullDisplay.jpg|First full image display. | ||
| + | Image:TileDriver-GammaCorrection.jpg|Gamma correction implemented and numerous bugs fixed. | ||
| + | </gallery> | ||
| + | |||
| + | [[Category:Dormant Projects]] | ||
Latest revision as of 15:15, 28 March 2021
TileDriver is a board to drive HUB75 type RGB matrix panels from an SPI bus. It contains a framebuffer and interface circuitry to allow slower CPUs like an AVR or PIC to drive the displays.
Project Status
- 2015-12-18: Started implementing the dual-port RAM controller (with an EBR RAM backend for simplicity in the first version, rather than SDRAM like the real one will use). Works reliably if the RAM controller clock is 4x the main clock, but not 2x like it should. At 2x it sometimes works and sometimes acts weird, likely some kind of phase thing. Needs more troubleshooting. Have also only tested it at human-visible clock rates, need to get the logic analyzer out and test it at tens of MHz still.
- 2015-12-01: Fixed the missing-MSB error, was actually in the ruby code not the hardware/verilog! The SPI clock phase in the code driving the Bus Pirate was wrong, so the MSB was getting chopped off. Fixed and gradients look good now.
- 2015-11-28: Many speed and usability improvements in tilesend, now takes any image format and puts it on the display. Implemented gamma correction which makes the image look much better overall. Discovered that brightness levels are "wrapping around" and anything >127 goes back to zero brightness and ramps up again from there, indicating an MSB is getting chopped off somewhere. Logically analyzing r_value_a it seems bits 0 and 1 are always the same, which also doesn't seem right. Ran out of time after this point, need to pick back up here next time. Wrote a quick 'tilegradient' tool to generate a 0-255 gradient for troubleshooting.
- 2015-10-03: Build a breakout board for the tile connection to enable hooking a logic analyzer up to all the signals. Got SPI-to-tile working for a full display! Using the internal EBR in the CPLD right now, still need to fix up a lot of messy code and get the framebuffer into the external SDRAM, but it's getting there.
- 2015-09-26: Got the first 3 bytes of RAM used to set the colour of the whole screen, which is a start.
- 2015-09-19: Got the BCM working so each colour can now be set to any brightness via the DIP switches.
- 2015-09-18: Got the basic hardware assembled on the MachXO dev board (connector for tile, 3x3 DIP switches to set colours for testing). Screen is successfully being driven with a single hardcoded colour over the whole display.
- 2015-09-16: Received 32x32 video tile and MachXO dev board to prototype this.
- 2015-09: Started putting idea together to use in the future BRCRD Scoreboard project.
Overview
- 640x640x24bpp max display size
- Main data input via SPI at up to 50MHz
- 256x256x24bpp can update at 30fps
- 640x640x24bpp can update at 5fps, still fine for static data displays
Gallery
First light from the TileDriver code on the dev board.
First successful BCM-based dimming.
First half image display.
First full image display.
Gamma correction implemented and numerous bugs fixed.
