Difference between revisions of "Project Checklists"
From Hackstrich
(Added check to make sure silkscreen on both sides is facing the same way.) |
(Added more detail on what "required test points" actually means.) |
||
Line 8: | Line 8: | ||
* Are any required protection devices (e.g. PTC resettable fuses) included? | * Are any required protection devices (e.g. PTC resettable fuses) included? | ||
* Are required test points included? | * Are required test points included? | ||
+ | ** One small SMD point on every net that could conceivably require troubleshooting and does not appear on a connector | ||
+ | ** At least one PTH ground test point for scope/logic analyzer probes | ||
+ | ** PTH test points for nets that are very likely to require extensive troubleshooting, if space is available | ||
+ | ** 8/16-bit test/debug bus connector for CPLD/FPGA projects that could require logic analyzer connection | ||
* Is there a way for the user to receive status information (like LEDs)? | * Is there a way for the user to receive status information (like LEDs)? | ||
* Are all nets named something useful (not N$)? Use the SHOW @ N$* command to check. | * Are all nets named something useful (not N$)? Use the SHOW @ N$* command to check. | ||
Line 15: | Line 19: | ||
* Are all connector pins rated for the current they will be carrying? | * Are all connector pins rated for the current they will be carrying? | ||
* Do all specified PMICs have appropriate input voltage ranges, power levels, and topologies? | * Do all specified PMICs have appropriate input voltage ranges, power levels, and topologies? | ||
− | * Are source/sink-only I/O connectors provided with the correct | + | * Are source/sink-only I/O connectors provided with the correct companion voltages? |
== PCB Completion == | == PCB Completion == |
Revision as of 22:24, 1 November 2017
Schematic Completion
- Does the schematic pass ERC?
- Is there a way to power the board?
- Is there a way to program any MCU/CPLD/FPGAs on the board?
- Are all clock signals routed to clock pins (if CPLD/FPGA)?
- Are all MCUs on the board clocked (if required)?
- Are required bypass capacitors included?
- Are any required protection devices (e.g. PTC resettable fuses) included?
- Are required test points included?
- One small SMD point on every net that could conceivably require troubleshooting and does not appear on a connector
- At least one PTH ground test point for scope/logic analyzer probes
- PTH test points for nets that are very likely to require extensive troubleshooting, if space is available
- 8/16-bit test/debug bus connector for CPLD/FPGA projects that could require logic analyzer connection
- Is there a way for the user to receive status information (like LEDs)?
- Are all nets named something useful (not N$)? Use the SHOW @ N$* command to check.
- Are all nets properly classed (if required)?
- Is there a way to set the address of the board (if on a multidrop bus)?
- If an Arduino-compatible shield, make sure a reset button and power LED are included.
- Are all connector pins rated for the current they will be carrying?
- Do all specified PMICs have appropriate input voltage ranges, power levels, and topologies?
- Are source/sink-only I/O connectors provided with the correct companion voltages?
PCB Completion
- Is the DRC engine set up to match the board house being used?
- Does the board pass DRC?
- Are all connectors set up so that they won't interfere with each other?
- Do a physical mockup if required to make sure everything fits in properly.
- Are all connectors on the correct side of the board?
- Has the footprint/pinout of any new components been double checked?
- Will the test points be easy to get to once the board is stuffed?
- Are all sharp bends mitered?
- Are all high-speed signals properly laid out?
- Is the ground plane set up properly?
- Are QFN/DFN/high-power parts properly thermally laid out?
- Will the board plug into a standard 0.1" perfboard/breadboard (if applicable)?
- Are mounting holes included if required?
- Is the required silkscreen all added?
- Connector/pin descriptions
- Board name
- Copyright/left information
- URL (if possible to fit)
- Revision number
- Area for serial number
- Strich
- Does text on both sides of the board all face the same direction?
CAM Completion
- Do drills line up with pads?
- Are vias tented appropriately?
- Does mask extend between component pins?
- Are test points left exposed?
- Do silkscreen layers look reasonable and non-overlapping?
- Does any silkscreen overlap drills?
- Are required ground ties in place (if required)?