Difference between revisions of "StrichLux/IO-SPI"
From Hackstrich
(Minor board silk issue.) |
(Status update) |
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== Project Status == | == Project Status == | ||
| + | * 2012-06-02: Lots of troubleshooting, not quite there yet. Was hanging after one cycle, which is now fixed/working in the simulator. Need to re-test against real hardware next time I'm at the lab. | ||
| + | * 2012-06-01: Assembled and started testing. | ||
* 2012-05-31: Boards are here! | * 2012-05-31: Boards are here! | ||
* 2012-05-24: Parts ordered and received. Still waiting for boards. | * 2012-05-24: Parts ordered and received. Still waiting for boards. | ||
| Line 18: | Line 20: | ||
== Rev. 1 Issues == | == Rev. 1 Issues == | ||
* Missing silkscreen on U1 | * Missing silkscreen on U1 | ||
| + | * TDO/TDI connect to the wrong pins | ||
| + | * SN needs to be tied high | ||
== Architecture == | == Architecture == | ||
Revision as of 04:37, 3 June 2012
The StrichLux IO-SPI module will provide one universe of SPI output for the StrichLux system, mainly for use driving addressable LED strips. Initially it will only support output, but the hardware supports output, so it could be implemented later.
Project Status
- 2012-06-02: Lots of troubleshooting, not quite there yet. Was hanging after one cycle, which is now fixed/working in the simulator. Need to re-test against real hardware next time I'm at the lab.
- 2012-06-01: Assembled and started testing.
- 2012-05-31: Boards are here!
- 2012-05-24: Parts ordered and received. Still waiting for boards.
- 2012-04-29: Finished schematic, done board layout, checklists run, sent to Laen for manufacturing. Parts still need to be ordered.
- 2012-04-28: Started schematicizing and BOM selection.
- 2012-04-24: Started initial planning.
Specs
- Based around the Lattice MachXO2-256 CPLD (common to other IO modules)
- Will pass power through from one of the high power busses
- Needs to handle 50W! (4.25A @ 12V or 10A @ 5V)
- JST SM seems to be a common connector for these
- But it's wire-to-wire only, no PCB mount version available
- Using a 2x3 Mini-Fit Jr. connector instead, 6 pins so it can carry a full SPI bus (MISO/MOSI/!SS/SCLK) plus power
Rev. 1 Issues
- Missing silkscreen on U1
- TDO/TDI connect to the wrong pins
- SN needs to be tied high
Architecture
<graph>graph {output: svg;}[ SPI Hardened Core ] <-- Wishbone --> [ Module Controller Softcore ]</graph>
